1. Field of Invention
The present invention relates to methods for operating a memory and a memory apparatus. More particularly, the present invention relates to methods and memory apparatus for reducing the second bit effect in memory apparatus.
2. Description of Related Art
A memory is a semiconductor device designed for storing information or data. As the functions of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. Consequentially, the demand for high storage capacity memories is getting more.
Among various types of memory products, a non-volatile memory allows multiple-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power to the memory is terminated. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipment.
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Conventional flash memory cells store charge on a floating gate. Another type of flash memory uses a charge-trapping structure, such as a layer of non-conductive SiN material, rather than the conductive gate material used in floating gate devices. When a charge-trapping cell is programmed, the charge is trapped and does not move through the non-conductive layer. The charge is retained by the charge trapping layer until the cell is erased, retaining the data state without continuously applied electrical power. Charge-trapping cells can be operated as two-sided cells. That is, because the charge does not move through the non-conductive charge trapping layer, charge can be localized on different charge-trapping sites. On the other words, in the flash memory devices with the use of the charge-trapping structure, more than one bit of information is stored in each memory cell.
A single memory cell can be programmed to store two physically separated bits in the charge-trapping structure, in the form of a concentration of charge near the source region and another concentration of charge near the drain region. Programming of the memory cell can be performed by Channel Hot Electron (CHE) injection, which generates hot electrons in the channel region. Some of these hot electrons gain enough energy to become trapped in the charge-trapping structure. By interchanging the biases applied to the source and drain terminals, the charge is trapped either in a portion of the charge-trapping structure near the source region, near the drain region, or both.
Accordingly, for example, if no charge is stored in the memory cell, the threshold voltage of the memory cell has a minimal value corresponding to a combination of bits 1 and 1. If charge is stored in the charge-trapping structure near the source region, but not near the drain region, the threshold voltage has a different value corresponding to a combination of bits 1 and 0, for example. The threshold voltage has yet another value if charge is stored near the drain region but not near the source region. In that case, the threshold voltage corresponds to a combination of bits 0 and 1. Lastly, if charge is stored near both the source and the drain region, the threshold voltage is at its highest, and corresponds to a combination of bits 0 and 0. Thus, four distinct combinations of bits 00, 01, 10 and 11 can be stored, and each combination has a corresponding threshold voltage. During a read operation, current flowing through the memory cell will vary depending upon the threshold voltage of the cell. Typically, such current will have four different values, each corresponding to a different threshold voltage. Accordingly, by sensing such current, the particular bit combination stored in the cell can be determined.
The total available charge range or the threshold voltage range may be referred to as memory operation window. In other words, memory operation window is defined by the difference between program level and erase level. A large memory operation window is desirable because good level separation between states is needed for cell operation. The performance of two-bit memory cells, however, is often degraded by the so-called “second bit effect” in which localized charges in the charge-trapping structure interact with each other. For example, during a reverse read operation, a read bias is applied to the drain terminal and the charge stored near the source region (i.e., a “first bit”) is sensed, then the bit near the drain region (i.e., the “second bit”), however, creates a potential barrier for reading the first bit near the source region. This barrier may be overcome by applying a bias with a suitable magnitude, using the drain-induced barrier lowering (DIBL) effect to suppress the effect of the second bit near the drain region and allow the sensing of the storage status of the first bit. However, when the second bit near the drain region is programmed to a high threshold voltage state and the first bit near the source region is at un-programmed state, the second bit raises this barrier substantially. Therefore, as the threshold voltage associated with the second bit increases, the read bias for the first bit becomes insufficient to overcome the potential barrier created by the second bit. As a result, the threshold voltage associated with the first bit is raised as a result of the increasing threshold voltage of the second bit, thereby reducing the memory operation window. The second bit effect decreases the memory operation window for 2-bit/cell operation. Therefore, there is a need for methods and devices for suppressing the second bit effect in memory devices.